ASIC Design Engineer

• 5+ years of experience as an ASIC Design Engineer• Experience in ASIC design flows and methodology including RTL, verification, synthesis, Static timing analysis (STA),• Expertise with Verilog and RTL design• Familiar with Primetime Static Time Analysis (STA)• Good programming/scripting skills: Tcl, python, shell Physical Design - Power Methodology engineerRun, synthesis, placement, CTS, routing, and complete other physical design tasks for PPA recipe tuningAnalyze timing reports and see how it the critical paths impact powerAnalyze area and instance count and vt reports across multiple blocks Skills- Use EDA tool-based programming and scripting techniques to automate and improve throughput andQuality- 5+ Hands on experience in floor planning, place & route, power and clock distribution, pin placementand timing constraints generation. • Good programming/scripting skills: Tcl, python, shell