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Overview:Job Description:Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our CPU core design team. As a high-speed physical design engineer you will develop, implement, and verify high-speed processor cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow for high-speed processor cores. Tasks involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals, and the development of high-speed customized logic cells. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization, 2.5D RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, physical verification (drc, lvs, antenna), debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex modem CPU Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications:Candidates must have 8-12 years of direct relevant experience in Physical Design, floorplanning, P&R, formal verification, and/or physical verification. This position requires 2-5 years of experience with STA closure and Place and Route. Exposure to ICC, Innovus, and/or Prime Time is needed. Hands on experience with the latest FinFet technologies (20nm and below) is needed. Education:Required - Bachelor's degree in Science, Engineering, or related field. Preferred Qualifications:8+ years of direct industry experience in the following areas:Physical DesignPlace & Route tool experience on Cadence Innovus and/or Synopsys ICC2Timing closure experience in Synopsys PTSIFormal verification experiencePhysical verification experienceMaster's degree in Electrical Engineering
- ID: #23795419
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State: California
San diego
92121
San diego
USA
- City: San diego
- Salary: $60 - $70
- Job type: Contract
- Showed: 2021-12-03
- Deadline: 2022-01-23
- Category: Et cetera