Vacancy expired!
- 5+ years of ASIC verification experience• Experience in System Verilog testbench development and UVM/OVM methodology is a must• Must have hands-on experience with IP/Unit/Block verification, along with SV-UVM based testbench development for at least 3 year• Excellent communication skills and demonstrate the desire to take on diverse challenges• In this role, you will:• Be part of a team working on verification of complex IPs and sub-systems that are part of modern SoCs• Define, document, and implement UVM verification environment including agents and scoreboards• Develop and execute functional and performance verification test plans, including opportunistic use of Formal techniques• Define and implement functional coverage and drive coverage closure• Triage and debug testbench simulation fails. Qualifications:• Minimum BS (EE or CS) required with 5+ years of relevant experience• 5+ years of experience working on functional verification of IPs or sub-systems that are part of CPUs, GPUs, caches, memory systems, interconnects, PCIe, USB, or related blocks.• 5+ years of hands-on experience with UVM/OVM and System Verilog through development of test bench components, generating directed and random stimulus, and coding cover points and assertions• Experience in debugging design and driving coverage closure• Knowledge of verification principles, testbenches, test plans, stimulus generation, and coverage• Experience in formal and/or performance verification a plus
- ID: #44502544
- State: California Santaclara 95050 Santaclara USA
- City: Santaclara
- Salary: $60 - $70
- Job type: Permanent
- Showed: 2022-08-01
- Deadline: 2022-09-26
- Category: Et cetera