ASIC Verification Engineer

17 Aug 2024

Vacancy expired!

ASIC Verification Engineer

Our client is looking to have a very strong ASIC Verification Engineer to join a team of verification engineers to complete unit, subsystem and chip level verification. The person will be working closely with the executive team to design of state of the art SOC s that drive high performance computing and new server architecture.

Scope:

  • Test plan and development of the test bench and verification of high-performance SOC subsystems
  • Develop and maintain methodology/flows/checks for verification team
  • Work with multi-disciplinary groups to deliver verification tests and port in tests in the lab for post silicon validation
  • Verification of multi-million gate ASICs with System Verilog/UVM

Required:

  • Minimum of 5+ years of ASIC verification experience
  • Experience or knowledge of system architecture, CPU & IP integration, power and clock domains
  • Expertise in System Verilog and other high level language like C, C is a must
  • Familiarity with scripting in Python or Perl
  • Hands on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
#Dice-SPG

#Zip-SPG

#Mon-SPG

#CB-SPG #IND-SPG

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit

https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.

  • ID: #44946347
  • State: California Austin 00000 Austin USA
  • City: Austin
  • Salary: Competitive
  • Job type: Permanent
  • Showed: 2022-08-17
  • Deadline: 2022-10-15
  • Category: Et cetera