ASIC/FPGA Design Engineer

19 May 2024

Vacancy expired!

Bachelor's degree in electrical engineering, computer engineering, or other engineering discipline 2+ years of experience with Vivado or other FPGA development software 2+ years of experience in SystemVerilog, Verilog, or VHDL RTL design 2+ years of experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C, Perl, Tcl, Make, Bash Familiarity with a Continuous Integration Too Experience in designing data path and control RTL blocks

  • ID: #41158714
  • State: California Mountainview 94043 Mountainview USA
  • City: Mountainview
  • Salary: USD TBD TBD
  • Job type: Permanent
  • Showed: 2022-05-19
  • Deadline: 2022-07-18
  • Category: Et cetera