ASIC/FPGA Design Engineer

ASIC/FPGA Design Engineer: We are looking for FPGA Design Engineers for both contract and Full time positions for our client in Sunnyvale, CA. Successful ASIC/FPGA Design Engineer procures: Perfect understanding on DSP Design, implement and integrate 5G Protocol Stack layers from source models In addition to the above, block level micro-architecture design, RTL coding, simulation, and documentation gives us good FPGA designer. Decoding the models written in either C/C, MATLAB, or Python Scripting and automate workflows in Python, Tcl, and GNU Make(Source controls) - 2+ years of experience with Vivado or other FPGA development software - 2+ years Hands on experience in SystemVerilog or Verilog - 2+ years of experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C, Perl, Tcl, Make, Bash - Good knowledge on Continuous Integration Tool as well as Linux/Unix systems - Experience in designing data path and control RTL blocks - 2+ years of experience in designing as well as Theoretical knowledge on basic concepts in DSP or digital communication system blocks (e.g. filters, transforms, PHY blocks, loops, FEC, etc.)