ASIC/FPGA Verification Engineer

26 Mar 2024

Vacancy expired!

Job Title: ASIC/FPGA Verification Engineer

Location: San Jose, CA

Duration: 6+ months (Possible Extension-Long Term Project)

Rate: $115/hr on w2

Description
  • Participate in internal design and code reviews
  • Setup complete verification environment
  • Develop test plans and creating tests
  • Perform code and functional coverage and analyze coverage reports
  • Setup and run gate level simulations with SDF

Requirements
  • Master's degree
  • 7 years of ASIC/FPGA verification experience using one of the common verification methodology (i.e. systemVerilog, UVM)
  • Hand-on experience with code and functional coverage
  • Hand-on experience with gate level simulation
  • Familiar with high speed interface protocols is a plus
  • Good oral and written communication skill

  • ID: #49554533
  • State: California Sanjose 95101 Sanjose USA
  • City: Sanjose
  • Salary: $100 - $115
  • Job type: Contract
  • Showed: 2023-03-26
  • Deadline: 2023-05-23
  • Category: Et cetera