Design Verification Engineer job vacancy

Vacancy expired!

Design Verification Engineer

Full Time

Location: Sunnyvale, CA ( can start remote but relocate when Client opens their offices for work)

7-15 yrs of experience

Good UVM, System Verilog, Verilog

Strong UVM/SV skills.

Creating independent VIPs, creating TBs, sequence/driver/checker/monitor, etc.

Strong verification skills.

Good debugging skills

Strong scripting skills

Medium C-DPI based coding skills.

Experience with writing verification/test plan, coverage tracking and closure.

Good communication skills and team player. Should be able to independently communicate with design/arch team.

Strong problem-solving skills and get-it-done attitude. (Can’t stress on this item enough)

Experience/Knowledge with math blocks involving fixed point numbers. (Recommended, but not a MUST)

Experience in block level verification.

Some experience/understanding of chip level verification using UVM. (Recommended, but not a MUST)

Karan Seth

Recruitment Manager

Phone no.:

Email: LinkedIn - https://www.linkedin.com/in/karan-seth-53b41370/