Design Verification Engineer

31 Oct 2024

Vacancy expired!

  • Experience in System Verilog and C programming & Need UVM, can convert test plan into executable tests
  • Prior experience with SOC/Memory based systems a plus
  • Excellent debugging skills using VCS and Verdi
  • Should have used VCS/DVE

  • ID: #21960587
  • State: California Sanjose 95101 Sanjose USA
  • City: Sanjose
  • Salary: Depends on Experience
  • Job type: Contract
  • Showed: 2021-10-31
  • Deadline: 2021-12-27
  • Category: Et cetera