Design Verification Engineer

Amick Brown is seeking an experienced

• Responsibilities includes starting from testplanning to closing verification using coverage metrics.
• Involves testbench development from scratch or modification to existing testbench infrastructure for verifying new features.
• Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model.
• Directed/constrained random test generation, failure analysis and resolution, coverage analysis.
• Debugging failures, bug tracking, and analyze and close coverage.

• Advanced knowledge of HVL methodology (UVM).
• Expertise in HVL and HDL (SystemVerilog, Verilog).
• Experience defining coverage space and writing coverage model.
• Experience with SystemVerilog Assertion (SVA) is a plus.
• Team player with excellent communication skills and the desire to take on diverse challenges.
• Experience writing scripts in languages such as Perl/Python.
• Solid verification skills in problem solving, constrained random testing, and debugging.
• Experience with Veloce or other HW acclerators and Formal is a plus.

• Health
• Vision
• Dental
• 401k with company match
• Paid time off
• Sick Leave
• Short-Term Disability
• Life Insurance
• Wellness & Discount Programs