Design Verification Engineer

Responsibilities:

• Familiarity with ASIC, Computer and Embedded Systems Architectures
• Excellent oral and written communication skills with people at all levels, a must.
• Team player, with excellent debugging skills
• Skills/Experience

• Writing and maintaining test plans
• Creating and maintaining UVM test benches
• Created a module test bench from scratch
• Written Cover points, Assertions (SVA) and closed coverage o Knowledge of standard bus protocols such as AHB, AXI, etc.
• Scripting and test automation for regression o Experience with PCIe/NVMe and/or ONFI
• Experience with SSD architecture

• BS/MS in EE/CE, plus 5+ years of Design Verification experience