Vacancy expired!
- As a Design Verification Engineer you will contribute to the functional verification of GPU IP.
- This is a hands on role, driving next generation product development with a high level of contribution and knowledge base needs.
- GPU top level verification test plan development and execution:
- Work with RTL and unit level DV teams to develop test plans.
- C, SV/UVM stimulus development using constrained random and directed test flows.
- Functional coverage development and overall coverage closure.
- Develop and maintain SV/UVM components for GPU top level test bench and flows.
- Debug, maintain and track GPU level functional regressions.
- Support SOC, emulation and silicon teams in debugging functional failures.
- BSEE, Computer Engineer or comparable and 5 + years of DV experience
- Advanced knowledge of GPU and/or CPU architecture.
- Experience with SV/UVM, C, Verilog, Verdi, and coverage flows.
- Experience with debugging in a full CPU or GPU top-level design.
- Proficiency with scripting languages (Python, Perl).
- Excellent communication skills and ability to work with cross-functional teams.
- ID: #49554561
- State: California Sanjose 95101 Sanjose USA
- City: Sanjose
- Salary: $90 - $100
- Job type: Contract
- Showed: 2023-03-26
- Deadline: 2023-05-23
- Category: Et cetera