Vacancy expired!
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Logic BIST design and debug experience
- Well-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
- The ability to work in a multi-disciplined, cross-department environment
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
- Excellent problem solving, debug , root cause analysis and communication skills
- Experience working on ATE is a plus
- ID: #49245750
- State: California Sanjose 95101 Sanjose USA
- City: Sanjose
- Salary: Depends on Experience
- Job type: Permanent
- Showed: 2023-02-16
- Deadline: 2023-04-14
- Category: Et cetera