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FPGA Design and Debug:
- Logic Design and Simulation using Verilog (System Verilog is optional)
- HW Debug of FPGA using Chipscope or protocol analyzer
- Proficient with Xilinx or Intel/Altera FPGA Toolset for syntheses, place and route, timing closure)
- Good understanding of Fundamentals of digital logic design and computer architecture.
- Proficient with at least 1 protocol : PCIE, SATA, SAS
- Familiarity with TCL or other scripting language strongly preferred. Additional coding experience with "C", PERL, shell scripts considered a plus
- ID: #23691215
- State: California Sanjose 95101 Sanjose USA
- City: Sanjose
- Salary: $90 - $100
- Job type: Contract
- Showed: 2021-12-01
- Deadline: 2022-01-29
- Category: Et cetera