FPGA Designer

Quick summary of skillsets for both FO spots:

• Demonstrated experience with FPGA design using VHDL
• Transceiver design experience for high-speed/bandwidth interfaces (e.g. SERDES, Ethernet, PCIe, JESD etc.)
• FPGA design experience with large data manipulation / throughput (e.g. FIFOs, BRAM, streaming-to-memory map, etc.)
• Strong understanding of clock-domain-crossing, timing constraints
• System Verilog for Verification
• Familiarity with Linux OS, Make files

• Local to SD, onsite support for Lab debug, familiar with Lab debug strategies (e.g. scopes, ILAs, etc.)
• Familiar and/or experience with Mathworks Simulink HDL Coder

• Recent experience with Altera Quartus tool flow
• Familiar with Quartus SignalTap for FPGA debug
• Familiar with Avalon Bus Interface
• Design experience with Arria, Cyclone devices

• Recent experiance with Xilinx Vivado tool flow
• Familiar with Xilinx debug cores (ILA, VIO, IBERT)
• Familiar with AXI Bus Interface
• Familiar and/or design experience with MPSoC devices