10 Full-Time Positions - RTL Designer PCI/ RTL Designer Risc V (100% remote considered), to work with a company at the forefront of hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence.

03 Dec 2024

Vacancy expired!

10 Full-Time Positions -

RTL Designer – PCI/ RTL Designer – Risc V (100% remote considered), to work with a company at the forefront of hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence.

Position 1::::RTL Designer – PCIFull time opportunity in Campbell, CA (100% remote considered)Responsibilities
  • Develop and execute: micro-architecture specification, RTL in Verilog/System Verilog, performance, speed, power goals, and verification
  • Bringing up the chip in lab and developing bring-up scripts
  • Participate in chip architecture definition, review, verification, and testing
Requirements
  • BS/MS in Electrical Engineering or Computer Engineering with 5+ years of relevant experience from design to successful tapeouts and shipping
  • 5+ years of RTL design
  • Experience integrating 3rd party PCI IP into an ASIC design.
  • Experience working with PCI Gen 5 a plus
  • Experience in ASIC DFT and physical design flows and methodologies in 7nm – 16nm process nodes
  • Must be familiar with ASIC design tools and/or FPGA design tools
  • Experience with Xilinx Vivado a Plus
  • Experience programming in Python and/or C a plus
  • Self-motivated and able to work effectively independently and in a team

Position 2::RTL Designer – Risc VFull time position in Campbell, CA (100% remote considered) Responsibilities
  • Develop and execute: micro-architecture specification, RTL in Verilog/System Verilog, performance, speed, power goals, and verification
  • Bringing up the chip in lab and developing bring-up scripts
  • Participate in chip architecture definition, review, verification, and testing
Requirements
  • BS/MS in Electrical Engineering or Computer Engineering with 5+ years of relevant experience from design to successful tapeouts and shipping
  • 5+ years of RTL design experience
  • Experience integrating embedded CPU’s into an ASIC design.
  • Experience integrating 3rd party Risc V IP core into a design a plus.
  • Experience in ASIC DFT and physical design flows and methodologies in 7nm – 16nm process nodes
  • Must be familiar with ASIC design tools and/or FPGA design tools
  • Experience with Xilinx Vivado a Plus
  • Experience programming in Python and/or C a plus
  • Self-motivated and able to work effectively independently and in a team

  • ID: #23785957
  • State: California Campbell 95008 Campbell USA
  • City: Campbell
  • Salary: Depends on Experience
  • Job type: Permanent
  • Showed: 2021-12-03
  • Deadline: 2022-01-28
  • Category: Et cetera