Functional Verification Engineer

17 Aug 2024

Vacancy expired!

Functional Verification Engineer

This role requires and engineer to create an ASIC/RTL infrastructure that allows the design team to create high functional coverage simulations with relative ease. This person will create test benches as golden references for the team to build its unified simulation strategy. This person should be a subject matter expert and be able to create an infrastructure that allows a relatively new team of engineers to build their future work off of. This person will use up to date industry standards to deliver the most effective and efficient test benches.

Required:

Focused on creating functional simulation using Verilog and VHDL.

Automated functional simulation with the use of standard modules like DDR, PCIE, USB, I2C, SPI, AXI bus functional models, etc.

Scripting in Python. Others scripting languages could be acceptable for strong candidates but Python is preferred.

Vivado simulation experience. (6 months at a minimum. If they are experienced with ModelSim, Synopsis, etc. but have some working knowledge of Vivado that would be acceptable).

Pluses:

Regression test suite experience. Someone who has launched something with Jenkins would be a plus.

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Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

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https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.