Lead DFT Engineer (Design for Test)

Responsibilities:

• Support and work closely with automotive customers (with special emphasis on in-system
• test using LBIST & MBIST) and non-automotive customers in defining the ASIC DFT
• requirements and specifications
• Development and Implementation of DFT Architecture
• Design and Verification of DFT logic and components
• Generation of structural test vectors, analysis and coverage improvement
• Generation of timing constraints for the various DFT modes
• Work with design and implementation teams on DFT STA, logical, physical and power issues
• Support ATE team with test vector porting, diagnosis and physical failure analysis.

• Minimum of 15 years hands-on work experience in ASIC DFT design. Experience in an SoC
• product development organization or in an ASIC vendor company along with customer
• facing experience preferable
• Strong working knowledge of Chip design, Verilog/System Verilog and design verification
• Expertise and knowledge about DFT methodologies, industrial standards and practices
• Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and
• Boundary scan.
• Experience with DFT/ATPG EDA tools like Tessent/TestMax/Modus. Experience with
• simulators and waveform debug tools.
• Experience with STA tools like Primetime, SDF generation and Gate-level simulations
• Understanding and expert handling of Verilog HDL based Netlists, design libraries and
• Scripting (Perl/Tcl/)
• Minimum of 15 years hands-on work experience in ASIC DFT design. Experience in an SoC
• product development organization or in an ASIC vendor company along with customer facing experience preferable.
• Strong working knowledge of Chip design, Verilog/System Verilog and design verification
• Expertise and knowledge about DFT methodologies, industrial standards and practices
• Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and
• Boundary scan.
• Experience with DFT/ATPG EDA tools like Tessent/TestMax/Modus. Experience with
• simulators and waveform debug tools.
• Experience with STA tools like Primetime, SDF generation and Gate-level simulations
• Understanding and expert handling of Verilog HDL based Netlists, design libraries and
• Scripting (Perl/Tcl/)

• BS/MS in Electrical Engineering, Computer Science, or related field