Openings on Silicon Design Engineering Role - Full time / onsite

01 Dec 2024

Vacancy expired!

Looking for Silicon Design/Validation/Test Engineers, interested, ; Position 1 : Tech Lead Silicon Engineering Location : Austin, Sunnyvale, Redmond Job Description : Experience Required 10+ Years Technical/Functional Skills : Should have executed at least one Full chip Project (RTL2GDSII) Familiarity with Design (Front End and Physical Design) Flows, particularly Synopsys Hands on experience with any one or many of the following areas: Design, Verification, Synthesis and STA, DFT Roles & Responsibilities Responsibilities will be aligned with the technical skills mentioned above. Full chip project delivery, Technical leadership Position 2 : Silicon DIGITAL DESIGN Engineer Location : Austin, Sunnyvale, Redmond Job Description : Experience Required : Minimum 3 Years. Max 10 Years Technical/Functional Skills : Should have executed at least one Full chip or FPGA project. Should have done Architecture Design / RTL / Integration involving Processor, memory, IO, IP subsystems for SoC Familiarity with Front End Design Flows, Synopsys is preferable Gate count and performance estimation Position 3 : Silicon DIGITAL VERIFICATION Engineer Location : Austin, Sunnyvale, Redmond Job Description : Experience Required : Minimum 3 Years. Max 10 Years Technical/Functional Skills : Processor (c) based verification Constrained random verification using SV-UVM Tool usage and best practices for IP and IC level verification, preferably Synopsys HW-SW co-verification (SW running on uC) at IC design level for design signoff Verification scripting and database setup for regression analysis Verification of Digital with Mixed Signal IP models including analog and RF IP macros/models Gate level timing simulations Assertion based Verification Formal Verification Coverage driven Verification Position 4 : Silicon DFT Engineer Location : Austin, Sunnyvale, Redmond Job Description : Experience Required : Minimum 3 Years. Max 10 Years Technical/Functional Skills : Test pattern generation with tools preferably Synopsys / Mentor ATPG Simulations and debug Stuck-at, Latch-up, etc. coverage analysis and optimization expertise Memory (BIST) testability Capacity to identify functional tests for corner test coverage Knowledge of target testers and capacity to define test-times possible Preparation of test coverage for future multi-site and other test-time reduction possibilities Prepare HW Test setup for Silicon eye

  • ID: #23693651
  • State: California Sunnyvaleaustinredmond 00000 Sunnyvaleaustinredmond USA
  • City: Sunnyvaleaustinredmond
  • Salary: USD TBD TBD
  • Job type: Permanent
  • Showed: 2021-12-01
  • Deadline: 2022-01-30
  • Category: Et cetera