Physical Design Engineer

HCL America Inc.
Sanjose, CA
04 Mar 2025

Vacancy expired!

Hello ,Please take a look at the below job role and let me know if you would like to apply.

Job Title :- Physical Design Engineer

Job Location :- Bay Area, CA/Austin, TX

:About HCLHCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for you, visit hcltech.com.

Job Role:-• Working on 10nm/7nm/5nm designs with various customers for deployment.• Expertise in solving custorner's problems for critical designs to achieve desired performance, area and power targets.• Responsible to develop flow and methodology for doing placement, CTS and routing.• Provide training and technical support to customers

Must have :-
  • floor planning (both chip level and block level),
  • power grid design, power/signal integrity signoff, EM/IR signoff
  • physical verification (DRC/LVS/Antenna), DFM closure
  • Working on 10nm/7nm/5nm designs with various customers for deployment.

Job Requirement:• Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage.• Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results.• Experience on Floorplan design, including placement of hard-macros, padring, power grid and custom analog routes.• Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements).• Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing).• Hands-on experience with FinFET technologies is an advantage

Qualification:• Typically requires minimum of 2-10 years of experience in Physical Design with mainstream P&R tools• BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering.• ME/M.Tech/Master Degree in VLSI or Microelectronics is a plus
  • ID: #49401016
  • State: California Sanjose 95101 Sanjose USA
  • City: Sanjose
  • Salary: Depends on Experience
  • Job type: Permanent
  • Showed: 2023-03-04
  • Deadline: 2023-04-14
  • Category: Et cetera