Vacancy expired!
Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage. Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results. Experience on Floorplan design, including placement of hard-macros, padring, power grid and custom analog routes. Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements). Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing). Hands-on experience with FinFET technologies is an advantage
- ID: #49572610
- State: California Sunnyvale 94085 Sunnyvale USA
- City: Sunnyvale
- Salary: USD TBD TBD
- Job type: Permanent
- Showed: 2023-03-28
- Deadline: 2023-05-26
- Category: Et cetera