6 positions- UVM Verification Engineer opportunities (100% remote considered) to work with hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence.

22 Jun 2024

Vacancy expired!

6 Full-Time positions

Position 1: Staff Verification engineer

Office Located in Campbell, CA ( 100 % remote considered)

Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed

Expertise is UVM and System Verilog is mandatory.

Expertise in functional coverage flows, property checking and Assertions.

Prior experience with VIP of multi-protocol Serdes

Prior experience with Protocol verification such as Ethernet, PCIe, DDR is mandatory.

Expertise in formal verification flows and techniques.

Strong communication and presentation skills.

BSEE/MSEE is required.

Position 2 : Staff Verification engineer

Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed

Expertise is UVM and System Verilog is mandatory.

Expertise in functional coverage flows, property checking and Assertions.

Expertise leading functional verification for embedded SoC systems based on processors such as ARM, X86 or RiscV.

Expertise with SoC verification flows, power simulations, power-on-reset verification.

Prior experience in System Interconnects such as ARM, good understanding of AXI protocols

Strong communication and presentation skills.

BSEE/MSEE is required.

Position 3: Staff Verification engineer

Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed

Expertise is UVM and System Verilog is mandatory.

Expertise in functional coverage flows, property checking and Assertions.

Prior experience with VIP of multi-protocol Serdes

Prior experience with Protocol verification such as Ethernet, PCIe, DDR, System Interconnect (NOC, NIC).

Strong communication and presentation skills.

BSEE/MSEE is required.

Position 4 : Staff Verification engineer

Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed

Expertise is UVM and System Verilog is mandatory.

Expertise in functional coverage flows, property checking and Assertions.

Prior experience with VIP of multi-protocol Serdes.

Prior experience with formal verification.

Prior experience with Protocol verification such as Ethernet, PCIe, DDR, System Interconnect (NOC, NIC).

Strong communication and presentation skills.

BSEE/MSEE is required.

Position 5 : Staff Verification engineer

Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed

Expertise is UVM and System Verilog is mandatory.

Expertise in functional coverage flows, property checking and Assertions.

Expertise leading functional verification for embedded SoC systems based on processors such as ARM, X86 or RiscV.

Expertise with SoC verification flows, power simulations, power-on-reset verification.

Prior experience in System Interconnects such as ARM, good understanding of AXI protocols

Strong communication and presentation skills.

BSEE/MSEE is required.

Position 6: Staff Verification engineer

Seeking a seasoned senior Verification Engineer with a minimum of 10+ year of experience to join our verification team. Person should have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Person will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage. Person should also be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.

Skills Needed

Expertise is UVM and System Verilog is mandatory.

Expertise in functional coverage flows, property checking and Assertions.

Prior experience with formal verification tools and flows

Strong communication and presentation skills.

BSEE/MSEE is required.

  • ID: #43472901
  • State: California Campbell 95008 Campbell USA
  • City: Campbell
  • Salary: Depends on Experience
  • Job type: Permanent
  • Showed: 2022-06-22
  • Deadline: 2022-08-13
  • Category: Et cetera