Vacancy expired!
Title: Post-Silicon Validation EngineerLocation: Palo Alto, CA (onsite)Duration: Long Term This is Development requirement, Linux device driver experience is must. Identified candidate should have deep understanding in one or more of the following IPs- ARM A55 based CPU
- LPDDR4
- ISP (ARM C71 based)
- DSP (Tensilica Q7 based)
- PCIe Gen4
- SGMII / XFI (1gig and 10gig ethernet with integrated Switch IP)
- Slow Speed peripherals (UART, I2C, SPI, eMMC, JTAG, CANFD)
- TDM
Candidate should also have- good programming experience in embedded C &
- good understanding of debugging an embedded platform during bring up. (This includes exp of using JTAG/TRACE32 Lauterbachs etc)
The typical functions of a post-si validation Engineer areunderstand the underlying IP/subsystem that they are going to functionally validateCreate a Validation test plan referring to the Pre-Si verification plan and other documentsWrite and debug the testcase on a Zebu platformWhen Silicon is back execute the test cases on silicon and debugProjecting coverage statsThe resource should have already gone thru. Bring-up and validation of the IP on silicon and should be familiar with the area that they are going to validate. For more information please contact:MastanPh: {732} 595 9070 9069
- ID: #43097882
-
State: California
Paloalto
94301
Paloalto
USA
- City: Paloalto
- Salary: Depends on Experience
- Job type: Contract
- Showed: 2022-06-16
- Deadline: 2022-08-14
- Category: Et cetera