Principal ASIC Design Engineer

04 Jul 2024

Vacancy expired!

Principal ASIC Engineer Needed / Bay Area / $200K +

This Jobot Job is hosted by: Kevin SzilagyiAre you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.Salary: $180,000 - $250,000 per year

A bit about us:

We are building the first latency optimized SoC for the Automotive and data/edge center. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come.

Low Latency has become the key enabler for Automotive and other real-time application and the current industry' state-of-the art is just not up to the task. We have been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC, to deliver unrivaled products to mission-critical and real-time applications.

• We are seeking a dedicated hands-on ASIC Design Engineer to help develop an ASIC for our automotive and Data Center artificial intelligence computing architecture• As an ASIC Design Engineer, you will be participating in Architecture definition and modeling, verification test plan and testbench.• You will be responsible for developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.• Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoC.• Define a micro-architecture for the implementation and the usage of the functional block IP, possibly with external sourced IPs.• Participate SoC level integration and verifications.• Work with the Physical design team for the timing closure

Why join us?
  • Amazing Compensation
  • Room for growth
  • Great Benefits

Job Details
  • 10+years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of general experience as an ASIC Digital Design Engineer for building complex SoCs.
  • Experience in converting a module-level micro-architecture definition from given Marketing requirements.
  • Expert in RTL Logic Design, CDC, RDC, Scan insertion, Lint, LEC., and synthesis with timing constraints.
  • Experience in low-power design with UPF.
  • Capable of writing System Verilog DPI-C and/or UVM Bench for unit/top-level integration tests.
  • Scripting experience with Tcl, Python (or similar) language.
  • At least gone through entire ASIC design phases; from micro-architecture to post-silicon bringing-up, and validation.
  • In-depth Knowledge of one of the parallel processing hardware architectures
  • Neural Network Computation Flow on GPU/NPU
  • Array/Vector/Systolic Processors
  • SIMD/SIMT Processing Pipelines
  • Base Jump manycore
  • GPU cache hierarch and Latency-hiding with NoC Inter-connect bus fabric

Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.

  • ID: #43826086
  • State: California Sunnyvale 94085 Sunnyvale USA
  • City: Sunnyvale
  • Salary: $180,000 - $250,000 per year
  • Job type: Permanent
  • Showed: 2022-07-04
  • Deadline: 2022-09-01
  • Category: Et cetera