Vacancy expired!
Candidate Roles and Responsibilities
• Collaboration with offshore team. • IC role and offshore task coordination • Must have 10+ yr experience with ASIC design activities – Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations. Preferred: • Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols. • Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must.- ID: #48850305
- State: California Californiacity 93504 Californiacity USA
- City: Californiacity
- Salary: $140,000 - $160,000
- Job type: Permanent
- Showed: 2023-01-27
- Deadline: 2023-03-13
- Category: Et cetera