Vacancy expired!
Job Title: RTL Design Engineer Location: Santa Clara, CA Roles and Responsibilities
- Collaboration with offshore team.
- IC role and offshore task coordination
- Must have 10+ Year experience with ASIC design activities Verilog RTL, test case debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations.
Preferred: - Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols. Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must
Education: Bachelor's Degree Thanks and Regards, Manish Sarswat Account Manager E: manish.s@e-solutionsinc.com 33 Wood Avenue South Suite 600, Iselin NJ 08830 www.e-solutionsinc.com https://www.linkedin.com/in/manishsarswat/ USA | CANADA | UK | SINGAPORE | MALAYSIA | INDIA Disclaimer: E-Solutions provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, amnesty, or status as a covered veteran in accordance with applicable federal, state and local laws. We especially invite women, minorities, veterans, and individuals with disabilities to apply. EEO/AA/M/F/Vet/Disability. RTL Design Engineer1ASIC,RTLN/AFull Time,ContractUnited States
- ID: #49419073
-
State: California
Sanjose
95117
Sanjose
USA
- City: Sanjose
- Salary:
USD
TBD
TBD
- Job type: Permanent
- Showed: 2023-03-07
- Deadline: 2023-05-05
- Category: Et cetera