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Job DescriptionAs a senior RTL Interconnect design engineer, you will work as part of a custom system coherentinterconnect IP team. This is a senior role, tasked with owning and driving the RTL design,performance and power optimization of key sub-blocks of the coherent interconnect and last levelcache (LLC). Solid engineer foundation and RTL design experience is desired for success.
Key responsibilities include: Own and drive key sub-blocks of the coherent interconnect or LLC Produce quality RTL on schedule meeting PPA goals Engage with others for PPA optimization Partner with the physical design and CAD team to resolve implementation level details Work closely with design verification to test plan and otherwise ensure proper functionality Deliver quality micro-architectural level documentationMinimum requirements: BSEE, Computer Engineer or comparable and 7 + years of experience Experience owning and driving the RTL design of various sub-blocks of the interconnect for the highperformance digital designs Demonstrated experience of successful Architectural through RTL design experience on highperformance digital designs Knowledge of in coherent interconnect and bus protocols Knowledge of memory subsystem design including cachesPreferred candidate will possess the following: Energetic, curiosity, and passion in logic design Good written and verbal communication skills Efficient digital design techniques Arm/AMBA interconnect experience preferred- ID: #49553204
- State: California Sanjose 95101 Sanjose USA
- City: Sanjose
- Salary: Depends on Experience
- Job type: Permanent
- Showed: 2023-03-26
- Deadline: 2023-05-20
- Category: Et cetera