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- Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable test benches from scratch.
- Develop Functional Coverage Models and Closing Code Coverage
- Utilize UVM to create drivers, monitors, predictors, and scoreboards.
- Minimum of 15 years’ experience in Digital ASIC verification with at least 5 years focused on UVM.
- Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using SystemVerilog.
- Experience with design architecture and detailed specification generation.
- All candidates MUST hold a bachelor’s degree (or higher) in Engineering.
- Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics, or chemistry (e.g., Bachelor) and typically 20 or more years' related work experience or an equivalent combination of technical education and experience (e.g., PhD+15 years' related work experience, Master+18 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
- ID: #49055711
- State: California Elsegundo 90245 Elsegundo USA
- City: Elsegundo
- Salary: $90 - $98
- Job type: Contract
- Showed: 2023-02-07
- Deadline: 2023-03-19
- Category: Art/media/design