Senior EDA Engineer

• Expertise in silicon design as relating to CPU systems, storage controllers, network ASIC and others.• Extensive understanding of SoC building blocks spanning scheduling, queuing, caching, power management, clock tree, and power domains.• Demonstrated experience in using AI algorithms to modify silicon design workflows.• Co-simulation experience of RTL with FW, MATLAB / System C models with RTL / FW will be needed.• Proficiency in C/C/Python in a Linux development environment is required.• Familiarity extending UVM verification methodology to open source-based simulations tools will be helpful.• Experience with open-source tools such as Verilator, ICARUS and KLEE • Mindset to resolve difficult technical challenges with no visible solutions will be needed.• Consummate team player with the ability to influence all levels of the organization is desired.