SerDes Characterization Engineer (analog ) - Santa Clara, CA

Job Title - SerDes Characterization Engineer (analog ) Location - Santa Clara, CA (onsite). Option for hybrid, but mostly will be working in the lab. Job Duration: 12+ months Description: Develop validation & characteristics (testing - silicon) in SerDes (PCIE, Ethernet), Python, key words - high-speed, Scope, BERT, VNA, Signal Integrity (SI), PHY, analog signal As a SerDes V&C team member, you will be part of industry-leading engineering team that is developing validation and characteristics solutions for the cutting-edge generation of transceivers. Successful candidates will work as part of a team on projects which may include: Validating PMA (or PHY) blocks of transceivers Development of automated testing scripts and scenarios Education Requirements Bachelor's Degree in EE, CS (is highly preferred, but not required. Will be looked at on case by case situation) or related fields with 5+ years of work experience, or, Master's Degree in EE, CS (is highly preferred, but not required. Will be looked at on case by case situation) or related fields with 2+ years of work experience Qualifications Hands-on experience with high-speed scope, BERTs, VNA and associated lab equipment for SERDES characterization Experienced in Python and automation techniques A team player with strong written and verbal skills Experienced in C/Verilog/FPGA design is a plus Familiarity with FPGA design flow is a plus