Sr. Staff Engineer, Digital Verification & Design

Job Description:The engineer will plan and execute unit/subsystem/system level design and verification. The engineer will actively work with designers and architects to understand and influence the unit's architecture, plan and implement design changes in Verilog.The engineer would build scalable and reusable testbenches in SystemVerilog/UVM, develop checkers, monitors, scoreboard, coverage models.The engineer would develop and execute the constrained random coverage driven verification plan and execute until quality criteria are met.Experience in coverage driven constrained random digital design verification.Significant experience in developing testbenchs using SV, UVM, OVM, VMM.Highly skilled in debugging complex testbenches and systems.Knowledge of microcontroller based testbenches and Firmware / Hardware co-verification (knowledge of ARM uC / AMBA bus is desiderable).Knowledge of one or more protocols like PMBUS, I2C, UART, SPI etc is desirable.Knowledge of one or more scripting languages, such as PERL, Python.Knowledge in C/C programming is desirable.Professional Exp:BS/MS with 3-5 years of work experience in design and verification of IP/SOCsExperience in System Verilog, UVM, OVM, VMM etcExperience in Scripting languages such as perl, python, shellExperience in Firmware debugging at RTL level.Should be able to work on IP/SoC verification tasks independently