Verification Engineer for Memory Controller

Title: Verification Engineer for Memory Controller Mandatory skills: ASIC development projects, software, firmware,Verilog, System Verilog, UVM,hardware development setting,SVA, formal,UVM testbenches, monitors, checkers, sequences, test benches,PYTHON, PERL,debug design, TB failures, logfiles, waveforms,DRAM controller, PHYs, memory models,verification flows, verification metrics Description: Significant UVM, SystemVerilog experience in complex test-benchesExperience working with DRAM controller, PHYs, memory models is preferredSignificant experience with general verification flows and metricsExcellent debug skillsWorking with big teams across multiple geographiesEXPERIENCE AND EDUCATION:7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong Verilog/SystemVerilog knowledgeHas developed or significantly changed components in UVM testbenches - monitors / checkers / sequencesSome experience with SVA or formal are preferred.Ability to debug design/TB failures using logfiles and waveformsKnowledge of scripting language (PYTHON or PERL)Strong analytical skills and attention to detail;Strong written and communication skills.Note :option to work remotely . VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.