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FPGA Design/Verification Engineers (2 needs)Formal verification experience, specifically UVM Required Skills-Experience with complex electronics and embedded systems, FPGA and hardware development.-FPGA design experience.-Vivado and Questa experience (or an equivalent tool set)-Minimum of 4+ years of SystemVerilog or Verilog/VHDL-Constrained random testbench development-Knowledge of digital design, development, and simulation. Equal Opportunity Employer/Veterans/Disabled Benefit offerings include medical, dental, vision, term life insurance, short-term disability insurance, additional voluntary benefits, commuter benefits and 401K plan. Our program provides employees the flexibility to choose the type of coverage that meets their individual needs. Available paid leave may include Paid Sick Leave, where required by law; any other paid leave required by Federal, State or local law; and Holiday pay upon meeting eligibility criteria. Disclaimer: These benefit offerings do not apply to client-recruited jobs and jobs which are direct hire to a client To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit ;/em> The Company will consider qualified applicants with arrest and conviction records.
- ID: #49380621
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State: Colorado
Denver
80201
Denver
USA
- City: Denver
- Salary: $70 - $90
- Job type: Contract
- Showed: 2023-02-28
- Deadline: 2023-04-22
- Category: Et cetera