ASIC Design Verification Engineer in Santa Clara CA

Job Description

• Work with design team to understand the design intent and bring up the verification plans and schedules
• Develop UVM test environment, test plan, and test cases based on design specification and verification requirements
• Initiate test plan review and verification reviews with the teams at every stage
• Debug test cases and report verification result to achieve the expected code/functional coverage goal
• Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
• Take dedicated ownership to execute block level verification
• Undergraduate degree or above in Electrical or Computer Engineering
• Proven teamwork skills
• Excellent analytical and problem solving skills
• Excellent oral and written communication skills
• Conversant with some programmable languages such as Verilog, SystemVerilog, Perl/Python/Tcl scripts, Makefile and C

• Experience in developing test benches using the UVM methodology.
• Experience in C/C and SystemVerilog
• Experience in scripting language such as Perl/Python/Tcl scripts
• Experience with code coverage, formal verification tools.
• Experience with MTI and/or VCS simulator. Experience with waveform viewing tools such as Verdi

• Undergraduate degree or above in Electrical or Computer Engineering

• Knowledge of AXI/AHB protocol.
• Experience on DSP core verification is a plus.

• How many years of UVM and SystemVerilog experience do you have?
• How many years of C/C and Linux/Unix experience do you have?
• How many years of AMBA(AXI) or PCIe experience do you have?