Vacancy expired!
- Able to design new or make improvements to verification test benches and test cases
- Designing with all aspects of Universal Verification Methodology (UVM) based verification methodologies
- Creating a detailed verification plan
- Architecting re-usable and scalable verification environments
- Applying coverage extraction, creation and implementation when needed
- Applying assertion based methodologies when needed
- Updating/creating regression management and verification closure reports
- Quickly identify verification holes using tools and methods
- Collaborative and good communications skills
- Excellent debugging and problem solving skills
- Capable of working independently on the assigned design activities with minimal supervision
- Work effectively with internal designers and external contractors
- Self-starting, Highly Self Motivating
- IP implementation & validation
- Scripting related to Perforce/Collabnet (Subversion)
- Supporting existing products that are released in to production
- Assist in team building locally and at other site
- Travel 10%
- Other duties as required
- Global ASIC/FPGA/IP Development Manager
- Relevant Project Manager
- HW/FW/SW Team Personnel
- Principal/Manager
- Engineering Management
- Product Planning & Development
- PLM, Systems Architecture
- New Product Introduction
- None
- Preferred Degree Qualifications: Bachelor of Science (BS) or Master of Science (MS) Degree in computer engineering or electrical engineering
- Preferred Years of Experience: BS+(5 to 8) years, MS+(2 to 5) years
- Experience verifying complex Application Specific Integrated Circuits/Field Programmable Gate Arrays (ASICs / FPGAs).
- Experience in ASIC / FPGA verification using C/C and/or System Verilog.
- Experience with verification methodology UVM
- Experience with building and setting up scalable simulation / verification environments.
- Experience with scripting (bash/csh, Perl, TCL, Python, Linux OS etc.).
- Languages – Verilog, VHDL, python,
- Web based, metadata related languages (html,html5,java)
- Tools: Xilinx Vivado, Intel(Altera) Quartus Prime (Std/Pro)
- Mentor Questa, Synopsys DVE(VCS-MX)
- Linux Operating System
- Ability to remain stationary for long periods of time;
- Able to work at a desk majority of the day
- Moderate lifting, 15-44 lbs
- Ability to use a computer keyboard and computer screen for extensive computer work (preparing documents spreadsheets and communications via electronic mail)
- Ability to regularly work a minimum of 40 hours per week
- Master’s Degree in Computer Engineering, Electrical Engineering or equivalent.
- Constrained Random Verification experience, highly desired.
- Any FPGA/ASIC design experience is a definite plus.
- Experience with any network protocols (OTN, Ethernet, FC, SONET)
- Familiarity with Design of large complex designs, iterative timing closure techniques, various constraint methodologies
- Familiarity with testing of complex designs, code coverage, functional coverage, assertions.
- Ability to focus on finding design issues, corner cases
- Ability to produce out of box ideas to make designs more robust.
- Successful and timely completion of project milestones
- Can do attitude. Seriously Hard worker.
- High energy individual, Internally motivated
- Able to work well within development organization
- Ability to multitask in a dynamic environment that includes working with changing needs and requirements
- Ability to work as a teamDevelop leadership abilities
- Desire to help others with technical issues
- Methodology – ASIC Design/Verification Flow
- Project management skills
- Demonstrates a wide degree of creativity and latitude
- Broader scope to interact at development and industry standards level