Staff Digital Engineer

Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit Contribute within a highly experienced team of engineers with extensive cross-functional skill sets Employ clocking controls, FSM design, low power techniques, and high-speed design concepts Participate in design, architecture, and verification reviews Cover digital backend design from synthesis, static timing and logic equivalent checking Creating documentation targeting design, verification, and test groups Assisting with new feature proposal, definition, documentation, and implementation Assisting with silicon bringup and debug