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job summary:
Randstad Engineering Solutions is searching for a Senior level FPGA/ASIC Verification Engineer to join our team. This position will be responsible for the verification of graphics and video processing or Module Manager FPGAs for display applications. We lead the industry with cost competitive, innovative technology that sets us apart from our competition and helps our customers make the most of their investment in our products. We are responsible for designing products for both commercial and military avionics as well as ground vehicles. We are looking for a passionate problem solver with experience in verifying complex devices that need to abide by the guidance of DO-254 using UVM and system Verilog. location: CEDAR RAPIDS, Iowajob type: Contractsalary: $55 - 60 per hourwork hours: 8am to 5pmeducation: Bachelors responsibilities:Industry: AvionicsDevelopment Processes: Structured (e.g. DO-178B like)Development Environment: abide by the guidance of DO-254 using UVM and system VerilogCommunication Skills:Excellent communication skills, should be comfortable asking questions an interfacing with team members and clientsPrecise written skillsLeadership Skills:Should be comfortable leading and taking ownership of a process and seeing it through to completionRequired Skills:Experience with UVM and System VerilogExperience with the guidance of DO-254Experience using FPGA simulation toolsExperience with On-Target Hardware VerificationThese would be a plus:Familiar with RTL coding in VHDLFamiliarity with digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closureFamiliarity with NSEU effects on volatile memory elementFamiliarity with interface protocols (ARINC 661, ARINC 818, H.264/265, PCIe, SMPTE, DisplayPort, Analog Video, LVDS, etc.) qualifications:- Experience level: Experienced
- Minimum 2 years of experience
- Education: Bachelors
- ID: #43827319
- State: Iowa Cedar rapids 52498 Cedar rapids USA
- City: Cedar rapids
- Salary: USD55 - USD60
- Job type: Permanent
- Showed: 2022-07-04
- Deadline: 2022-09-01
- Category: Et cetera