considerations
Spec comprehensive CDC/RDC check flows and work with CAD team to implement
Review and approve CDC/RDC constraints and Qualifications
Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design
- ID: #54271422
- State: Missouri California 65018 California USA
- City: California
- Salary: USD TBD TBD
- Job type: Full-time
- Showed: 2025-08-03
- Deadline: 2025-09-30
- Category: Architect/engineer/CAD