Senior VLSI Design Engineering (New College Grad, Masters)

Join us and jumpstart your career alongside our team of innovators and industry influencers and help shape the future of digital technology with a leading provider of flash memory and storage solutions! Please note: this posting is not for a specific job opening and by submitting your resume, you are expressing interest in being contacted about one of the following roles at Sandisk: Essential duties and responsibilities:  AI-Enhanced Chip Design – Design Engineers will be responsible for designing, developing, modifying and evaluating Chip architecture circuit structures for feasibility study of high-performance NAND flash, including new, most advanced 3-dimentional NAND memories. A design engineer will focus on developing technologies related to AI. In this role, you will be part of a multi-disciplinary team of researchers and software developers, working on designing, building, and deploying AI technologies and applications. Familiarity with AI/ML frameworks and the interworking of LLMs are a plus. Analog/Mixed-Signal Design - NAND Memory Design & Verification Engineers are responsible for designing, developing, modifying, and evaluating analog and mixed-signal integrated circuits (ICs) for high-performance NAND flash, including the most advanced 3-dimensional NAND memories. Engineers in this role will focus on building low-power analog modules such as OPAMPs, voltage regulators, reference generators, and charge pump circuits. You will also contribute to high-voltage word line driver design, sensing operation analysis, and power/ground network optimization. This role offers the opportunity to define chip architecture, floorplan and die size by cross-collaborating with multiple functions including layout, characterization, and silicon validation teams to bring innovative circuit designs from concept to production. High-Speed PHY and Interface Design - High-Speed PHY and Interface Design Engineers will be responsible for architecting and implementing custom high-speed PHY and DataPath circuits for NAND interfaces and memory protocols such as DDR3/4/5, LPDDR4/5, GDDR, and HBM. In this role, you will focus on clock recovery, timing budgeting, SI/PI analysis, and analog/digital co-simulation across a wide range of speeds and topologies. The ideal candidate thrives in a multi-disciplinary environment, balancing deep theoretical understanding with practical implementation. Familiarity with Cadence Virtuoso, Synopsys tools, and Verilog/Liberty model development is a plus.   Physical Design Engineering - Physical Design Engineers will be responsible for logic synthesis, place and route (P&R), and timing analysis for NAND flash memory chips, ensuring designs meet performance, power, and area (PPA) targets. Engineers in this role will work closely with front-end RTL teams and back-end implementation engineers to perform physical verification, static timing analysis (STA), and tape-out readiness. You will apply deep knowledge of design principles and CAD tools to develop scalable physical design methodologies. Familiarity with scripting (e.g., Python, Perl, TCL) and an understanding of device physics in deep sub-micron technologies are a plus.   High speed Data Path & Circuit design Engineers - Circuit Design Engineers in this role will focus on developing and evaluating transistor-level and gate-level architectures for NAND flash memory, including page buffers, sense amplifiers, and high-speed datapath circuits and interface protocol design. You will architect and design digital and/or analog circuits, perform block level and full chip circuit simulations to meet all performance specifications. You will also contribute to RTL design, verification, clock domain crossing (CDC) and Prime time analysis. This role spans the full development lifecycle—from early feasibility and simulation to silicon probing and debug—requiring close collaboration with layout and characterization teams. Proficiency in HSPICE, FINESIM, and Verilog is essential, along with a strong foundation in analog and digital circuit fundamentals.