ASIC Timing Engineer

30 Jun 2024

Vacancy expired!

Our client in Yorktown Heights, NY and looking ASIC Timing Engineer.

This is a 6 months contract with possible extension.

We are looking for ASIC Timing Engineer

Task Description:
  • This engineer will assist in leading the effort towards achieving timing closure for an in-flight non-traditional ASIC to be released in the second half of the year.
  • This includes all tasks related to achieving timing closure on an ASIC design. Prior experience with both the Cadence Innovus Design suite and Tempus timing, as well as GlobalFoundries / Avera Semi / Marvell's FX14 ASICs Dflow is a must.
  • Experience is required in setting up and running with Tempus DSTA , working on hierarchical designs both at the top-level as well as macro (i.e. block) level, and understanding all necessary PDK models used for timing (i.e. dotlibs).
  • The selected candidate will be required to work both independently and collaboratively in conjunction with other teams across client Research.
  • As such, the ability to be a hands-on person is critical, capable of running tools, working effectively with others, while having the willingness and ability to learn new tools. Similarly, a strong understanding of the underlaying concepts is required to allow for early modeling techniques in the absence of fully developed designs or fully defined parameters.
  • An intimate knowledge/use of scripting languages such as TCL and/or Python to facilitate such tasks is required.

Job Duties:
  • Understanding and debugging SDC timing constraints both at the block and chip level.
  • Assist in generating ETMs (Extracted Timing Models).
  • Assist Physical Designers on running static timing analysis tools in Innovus.
  • Lead the effort in running static timing analysis in Tempus (i.e. graph-based and path-based analysis), at the block and Chip level, using distributed timing (DSTA) for the Chip level.
  • Facilitate generating and parsing timing reports via scripts to more effectively identify timing fails.
  • Assist in coming up with fixes in the form of PD scripts and or tempus ECOs for any timing problems.
  • Assist in generating back-annotated SDF files, used for simulations and detailed power analysis.

Required skills/Level of Experience :
  • All tools necessary to close timing on a complex ASIC
  • Strong verbal and written communication skills required.
  • Extensive experience as an Electrical / Computer Engineering, 5 years
  • Equal Opportunity Employer: Eclaro values diversity and does not discriminate based on Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status. If you are interested in this opportunity, please send me your updated resume in word format or call ASAP so that we can discuss it in more detail.

    I look forward to speaking with you!

    Thanks & Regards,

    Eric

    Phone:

    Mobile: Email:

    www.linkedin.com/in/ericeclaro

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    Eclaro 450 Seventh Avenue, Suite 1102, New York, New York 10123eclaro.com

    • ID: #43718261
    • State: New York Yorktownheights 10598 Yorktownheights USA
    • City: Yorktownheights
    • Salary: Depends on Experience
    • Job type: Contract
    • Showed: 2022-06-30
    • Deadline: 2022-08-26
    • Category: Et cetera