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As a part of the verification team, you will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform hands-on verification. Using your UVM and System Verilog coding and problem-solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
Qualifications BTech/BE/MTech/ME/MS - Electronics/Telecommunication/computer science or equivalent 2 to 5 years of experience in IP level or SOC level verification using System Verilog and OVM/UVM A solid understanding of object-oriented concepts and experience designing class-based test benches Should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon. Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers Expert in using verification tools like VCS, modelsim, etc Expert in System Verilog Assertions, Code and Functional Coverage and Formal verification techniques. Should have experience in regression debugs, Coverage analysis Expertise in scripting languages such as PERL, TCL, Python. Ability to communicate with architecture, RTL design and other remote teams Excellent verbal and written communication skills Protocol Knowledge on PCIe, Cache Coherency, Ethernet and DDR3/DDR4 is an added advantage.