Design Verification and Gate Level Simulation Principal Engineer

Career Opportunity: Job Title: Design Verification and Gate Level Simulation Principal Engineer About CodeForce 360 Making a career choice is amongst the most critical choices one can make, and it's important for the choice to be calculated with factors such as a company's run of success since its inception and more. But, when you come across a company that has reputation proven with nothing but an illustrious run of success since the day it began, you don't need to think of anything else. That's precisely what some of our employees and prospective employees think when they came across CodeForce 360. Position Overview Design Verification and Gate Level Simulation Principal Engineer Requirements:

• The ideal candidate should have 3-5+ years of Gate-Level Simulation experience.
• Expertise with debugging in Best/Worst SDF with min/max corner simulations.
• Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams.
• Experience with timing constraints and multi clock domain design
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
• Engage with the team to drive continuous improvement to the verification env to find more bugs and improve coverage
• Work as a team to grow together. Mentor and coach junior team members
• Power-Aware simulation experience is desirable.

• C (Programming Language) (P3 - Advanced)
• C Programming Language (P3 - Advanced)
• Industry X IOT Applications (P3 - Advanced)
• PERL Scripts (P3 - Advanced)