Vacancy expired!
- 1 person with Emulation model build, transactor integration, and debug experience (Zebu or Palladium) –
- 1 person with transactor development for testing on Zebu or Palladium –
- ASIC/IP RTL to Emulation platforms (Preferred: Zebu, Palladium)
- Build a model from the released RTL
- Generate target platform loadable image(s) test and release the image to Firmware and DV teams
- Run sanity tests for qualifying release of the image(s)
- Release the model to various teams including the Functional Validation team, Firmware, DV
- Assist debug of failures by providing an instrumented model ( Waveform Dumps, in-circuit debug) and interfacing with stakeholder
- Coordinate with Tools team to validate tool and Model release
- FPGA and Emulator flows and methodologies
- Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration