Vacancy expired!
- Designing and testing DSP-based, high speed FPGA designs
- Designing and supporting top-level digital communication design and system simulations
- Translating requirements into FPGA/waveform architectures
- Implementing and documenting FPGA designs using HDL (System Verilog, VHDL, etc.)
- Supporting systems integration and Test Engineering to produce functional design
- Producing simulations of and designs for both channel improvement measures, such as spectral bandwidth efficiency, and user density improvement measures, such as interference mitigation/cancellation, multiuser detection, and phased array antenna techniques
- Designing the implementations for further advances in adaptive TDMA, SCPC return channels.
- Designing and the implementation of anti-jam DSP techniques implemented in FPGA logic.
- Writing internal and external facing documents about iDirect Government physical layer FPGA technology
- FPGA design experience using Verilog, VHDL or System Verilog language targeting Xilinx/Altera FPGA's
- Knowledge of DSP and digital communications. Understanding of time domain versus frequency domain analysis, filter structures, and modulation/coding algorithms. Ability to describe and architect trade-offs for resource-limited systems.
- Experience Matlab/Simulink or equivalent for development of DSP algorithms implemented in FPGA's
- Ability to plan/perform analysis, studies/trade-offs in support of subsystem specification and hardware, FPGA, and software design recommendations.
- Experience in RF lab, including network setups (switches, cables, amplifiers, and filters) and signal analysis (Spectrum Analyzers, Network Analyzers, signal generators, etc.)
- Additional experience in the following areas is a plus:
- Experience with digital communications and control theory - stability and feedback control
- Extensive experience with both Altera and Xilinx design and verification tools
- Experience with Xilinx and Altera System-on-Chip devices: Xilinx Zynq-7000, Xilinx Zynq MPSoC, Altera SoC FPGA
- Background in RF chain design and considerations
- Background in anti-jam methodologies and design considerations
- Experience with C/C, bash, Python programming, etc.
- Experience with Xilinx and/or Altera high level synthesis tools
- Experience in an Agile/Scrum environment
- Satellite Communication experience