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- Understand complex architecture spec and develop a new testplan / review existing test-plans to provide feedback on missing test-cases
- Reviewing Architecture and Microarchitecture specs to identify holes
- Systemverilog and UVM expertise for developing a testbench
- Multiple years of experience in development of testbench, running/debugging tests, driving coverage closure
- Possibility of working with Formal Verification Tools
- Experienced with verification SoC/block level verification and has vast experience in testplan development
- Recent experience in SystemVerilog based testbench development and has a good hold on SystemVerilog coding
- Strong verification mindset for developing testplans by reading a hardware specification
- Experienced with Formal Verification Tools such as SLEC
- Perl/python scripting (nice to have)
- ID: #44912687
- State: Washington Mountainview 00000 Mountainview USA
- City: Mountainview
- Salary: Competitive
- Job type: Permanent
- Showed: 2022-08-16
- Deadline: 2022-10-14
- Category: Architect/engineer/CAD