Vacancy expired!
- Understand complex architecture spec and develop a new test-plan / review existing test-plans to provide feedback on missing test-cases
- Reviewing Architecture and Micro-architecture specs to identify holes
- Systemverilog and UVM expertise for developing a testbench
- Multiple years of experience in development of testbench, running/debugging tests, driving coverage closure
- Possibility of working with Formal Verification Tools
- Experienced with verification SoC/block level verification and has vast experience in test plan development
- Recent experience in System verilog based test-bench development and has a good hold on Systemverilog coding
- Strong verification mindset for developing testplans by reading a hardware specification
- Perl/python scripting (nice to have)
- Experienced with Formal Verification Tools such as SLEC
- ID: #43480109
- State: Washington Redmond 98052 Redmond USA
- City: Redmond
- Salary: Depends on Experience
- Job type: Contract
- Showed: 2022-06-22
- Deadline: 2022-08-15
- Category: Et cetera